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Samsung led IBM, arm and other manufacturers to jointly weave "memory architecture"
Shenzhen HongYu Semiconductor Co., Ltd. / 2021-08-30 09:17:38

In addition to Intel and Cisco, various manufacturers have begun to cooperate to develop storage level memory solutions.

  the demand for storage level memory interconnection structure has been quite urgent

  at present, many suppliers have begun to work together to develop gen-z solution - a set of scalable high-performance bus or interconnection architecture to connect computers and memory.

  this gen-z alliance is an open, non proprietary and transparent industry standard organization. The agency said it believes that open standards can provide a more level playing field and effectively promote the promotion, innovation and adoption of new technological achievements.

  the members of this alliance currently include AMD, arm, Broadcom, Cavium, clay, Dell EMC, HP enterprise business company (HPE), Huawei, IBM, IDT, Lenovo, mellanox technologies, micron, MICROSEMI, red hat, Samsung, Seagate, SK Hynix, western data group and Xilinx.

  obviously, several important forces are absent. Yes, the first is Intel, the data center and server CPU supply giant. This is really curious. In particular, as another developer of xpoint, micron joined it. In addition, are there any other candidate manufacturers that have not joined? Yes, Cisco is not on the list. As a UCS server supplier, we think Cisco has obvious reasons to be interested in this new CPU memory interconnection architecture.

  gen-z needs to pool the memory concept

  according to our knowledge, "this flexible and high-performance memory design architecture can provide a peer-to-peer interconnection system, so as to easily access large-scale data while reducing the use cost and avoiding various bottlenecks that exist widely today." This should be able to further reduce the storage access distance to the memory access distance by using storage level memory and new programming and architecture design ideas, so as to achieve significant speed improvement. Memory semantic structure treats all communication as memory operations, including load / store, put / get and atomic operations often used by processors. Memory semantics can optimize the latency of load commands pointed to register storage by CPU to sub microsecond level. This is completely different from the block storage access mechanism that needs to be managed with complex and code intensive software stack.

  the alliance also announced that "the rise of low latency storage level memory and the need for rack scale resources mean that a new data access scheme must be introduced."

   as a basic idea, the memory layer is becoming more and more important, and the composability of rack scale needs to be combined with high bandwidth and low latency structure, and ensure seamless access to the existing ecosystem without modifying or adjusting the operating system.

  the alliance has announced several basic features of the gen-z interconnection scheme:

   high transmission bandwidth and low delay level are realized through memory semantic based and simplified interface. The expansion capacity of transmission bandwidth can range from tens of GB / s to hundreds of GB / s, while the delay from loading to using memory is less than 100 nanoseconds.

   support scalable memory pool and resources to realize real-time analysis and in memory applications.

  very high software compatibility, i.e. no changes need to be made to the existing operating system.

  scale can be covered from simple low-cost connection to high-capacity rack scale interconnection.

  the core specifications, including architecture and agreement, will be finalized by the end of 2016. In addition, gen-z alliance is also actively attracting new members. We may welcome its first batch of products in early 2017.

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